Silicon contacts form one of the more numerous features on semiconductor devices. The typical configuration of a silicon contact on a semiconductor device is that of a sub-micron width hole or via extending through an insulating layer having a thickness of one micron or more on the device to an exposed area on an electrically conductive underlying layer of silicon that forms the contact. In semiconductor device manufacturing, these silicon contacts are generally first coated with a thin film of metal or metal compound such as titanium (Ti) or titanium nitride (TiN) that forms the metallization layer over which is applied a conductive metal such as tungsten or aluminum, which fills the hole to form a conductor through the insulating layer.
A Ti/TiN film forms an effective bond and conductive interface with the silicon contact on which it is applied and also enhances the formation of the overlying blanket or planarization layer that will fill the hole. Where the planarization layer is tungsten, the process currently used for its application is that of CVD with a WF6 reduction by which the tungsten nucleates onto the TiN layer, filling the holes and vias, often by planarizing the surface with a blanket tungsten film. In such a semiconductor manufacturing process, the resistivity of the junction between the Ti/TiN film and the silicon contact at the bottom of the hole or via must be kept low. Oxides and other impurities on the surface of the silicon contact increase the resistivity of the contact, and therefore should be cleaned from the silicon surface at the bottom of the hole, particularly where the size of the contact is small.
Research has focused attention on methods of cleaning silicon contacts in these high aspect ratio semiconductor devices. Wet chemical techniques such as the multi-step processes and hydrofluoric (HF) acid dip processes are used as the current industry standard, but when the holes have dimensions of one-quarter micron or less, these wet cleaning methods often contribute particles that can contaminate the wafer as well as being less than fully effective in cleaning the contact surfaces at the bottoms of these deep narrow holes and vias.
In-situ methods of cleaning silicon contacts, that is dry cleaning methods where wafers containing the devices are cleaned in place in the processing machine in which the metallization is to occur, just prior to metal deposition, have been of extreme interest in that they can provide a particle free environment and reduce native oxide formation on the silicon contacts during transfer through atmosphere and into the deposition module. In-situ approaches of the prior art have, however, not been effective. One in-situ method of cleaning the surfaces at both the contact and via level has included a physical etching process using an inert gas such as argon (Ar) in a plasma. Such plasmas are typically created by oppositely biasing electrodes to move electrons through the gas, stripping gas atoms of their electrons to create a plasma of positive Ar ions. One of the electrodes is typically a cathode assembly on which the surface to be cleaned is mounted. The positive Ar ions that are created in the plasma are accelerated to the surface of the wafer by a negative bias applied to the wafer surface, where the ions strike the surface and thereby dislodge material from the wafer surface by momentum transfer to remove the material from the wafer. Plasmas are usually confined close to the surface to be plasma etched by the configuration of the chamber walls and other physical structure within the chamber or by magnetic fields that trap the plasma producing electrons over the surface to be etched.
Physical processes such as plasma etching produce bombardment induced damage to the surface of the wafer and to devices being formed on the wafer. In the past, maintaining a low sputtering voltage difference between the substrate and a dense plasma, a process called “soft etch”, has been sufficient to minimize some of the potential damage to the surface being etched, but with present devices having features on a sub-micron scale, these soft etch voltages can still impart enough energy to the ions to cause them to inflict damage to some of the devices on the wafers. One such soft etch process uses a plasma cleaning method in which the plasma is powered independent of the accelerating bias voltage, which provides separate control of the bias voltage to allow lower sputtering energy to be used while still maintaining a plasma that is adequately dense for the process to proceed efficiently where the features are not too small. Nonetheless, such low energy sputter cleaning processes still have several drawbacks for very high aspect ratio devices currently being manufactured. Physical processes such as sputtering can redeposit materials from sidewalls of such high aspect ratio holes and vias onto the contact areas at the bottoms. Further, sputtering yields on the contacts at the bottoms of the deep holes and vias are low, which makes the cleaning process inadequate or at least very slow.
The need to clean a semiconductor wafer surface while inflicting minimal damage from the energy of the sputtering ions has been approached with the use of high density low energy plasmas such as those produced by electron cyclotron resonance (ECR). ECR plasma sources, however, include microwave generators and other complex components that are expensive and occupy substantial space either at the cleaning site or at a somewhat remote location near the cleaning site. These ECR generators produce a high density plasma that is caused to flow downstream and against the surface of the wafer to be cleaned. Such plasmas are capable of contacting the surface of the wafer biased at a low voltage so that ions strike the wafer surface with energy sufficiently low to reduce surface damage. However, low sputtering yield and therefore difficulty in effectively cleaning contacts at the bottoms of vias has remained a deficiency of purely physical etching processes.
The low sputtering yield in particular has led to investigation of adding a diffusive, chemical component to the etch, such as a component of hydrogen radicals to provide a hydrogen-based silicon contact dry cleaning process. Hydrogen based cleaning using ECR plasma sources has demonstrated successful cleaning of silicon contacts using an Ar/H2 plasma prior to CVD-Ti deposition. But remotely located ECR sources suffer nonetheless from large size and complex and expensive equipment as discussed above.
In all of the above methods for dry cleaning, an RF bias was found necessary for propelling ions to the surface to effect the etching. Even the remote plasma, such as ECR plasma, has been found ineffective for removing oxides and silicon in the absence of an RF bias or significant ion bombardment by self-bias. RF bias generally includes a plasma-to-substrate bias potential of about 100–300 V, whereas self-bias generally occurs at a bias potential of at least 20 V.
In a cleaning process described in J. Ramm et al., “Low-Temperature In Situ Cleaning of Silicon Wafers with an Ultra High Vacuum Compatible Plasma Source” 222 Thin Solid Films 126–131 (1992) and in J. Ramm et al., “Hydrogen Cleaning of Silicon Wafers: Investigation of the Wafer Surface After Plasma Treatment” 228 Thin Solid Films 23–26 (1993), a hydrogen/argon gas discharge is established by applying a potential between a grounded substrate holder and a DC filament. The discharge is characterized by voltages of 20–35 V, such as 30 V, and high currents up to 100 A, such as 10–100 A. A significant part of the DC current flows through the Si substrate to the grounded substrate holder. This high electron current and associated ion bombardment heat up the substrate to about 200–400° C. The described cleaning process is applied to Si wafer preparation for subsequent epitaxial deposition processing. Thus, the application is specific to bare silicon wafers and does not address cleaning inside deep, high aspect ratio features. Consequently, the described process is not required to prevent charge-up damage as in the case of cleaning of contacts, where high current densities through the wafer result in damage to the semiconductor device.
Accordingly, there remains a need for a dry cleaning method and an apparatus for effectively cleaning high aspect ratio contacts, without damage to the devices, that provide benefits at least as good as those of an ECR source, but with much simpler equipment.
In addition, during the manufacture of silicon contacts, a layer of polycrystalline silicon, referred to as poly-Si, is grown on the substrate, and then a portion of the poly-Si is etched away by argon sputter etching. During this poly-Si etching step, silicon is deposited on interior surfaces of the etching chamber. This silicon residue creates a memory effect in which, during subsequent oxide etching of wafers in the same chamber, the etch rate of the oxide changes after a poly-Si etch. Several sacrificial wafers are first required to recover the etch rate of the oxide to a normal level. Processing sacrificial wafers to recover a process is a costly and impractical procedure. Therefore, an in-situ chamber cleaning method is needed to recover the baseline oxide etch process after a poly-Si etch process has been carried out in the same chamber.